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CY25245
Frequency-multiplying, Peak-reducing EMI Solution
Features
* Cypress PREMISTM SMARTSPREADTM family offering * Generates an electromagnetic interference (EMI) optimized clocking signal at the output * Selectable output frequency range * Single 1.25%, 2.5%, 5%, or 10% down or center spread output * Integrated loop filter components * Operates with a 3.3 or 5V supply * Low power CMOS design * Available in 20-pin Small Shrunk Outline Package (SSOP)
Key Specifications
Supply voltages: .......................................VDD = 3.3V 0.3V or VDD = 5V 10% Frequency range:............................ 13 MHz Fin 166 MHz Cycle-to-cycle jitter: ......................................... 250 ps (max) Output duty cycle: ................................ 40/60% (worst case)
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
[1, 2]
SSOP
X1 XTAL Input X2
CY25245
SDATA SCLK Serial Interface
Spread Spectrum Output (EMI suppressed)
X1 X2 AVDD MW0^ SDATA OR1^ SCLK GND OR2* SSON#^
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
REFOUT VDD GND IR1* IR2* SSOUT MW1* GND VDD MW2^
CY25245
3.3V or 5.0V
Oscillator or Reference Input
X1
CY25245
SDATA Serial Interface SCLK
Spread Spectrum Output (EMI suppressed)
Notes: 1. Pins marked with ^ are internal pull-down resistors with weak 250 k. 2. Pins marked with * are internal pull-up resistors with weak 80 k.
Cypress Semiconductor Corporation Document #: 38-07124 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 2, 2005
CY25245
Pin Definitions
Pin Name Pin No. Pin Type SSOUT REFOUT X1 X2 SSON# MW0:2 15 20 1 2 10 4, 11, 14 O O I I I I Pin Description Output Modulated Frequency. Frequency modulated copy of the input clock (SSON# asserted). Non-modulated Output. This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#. Crystal Connection or External Reference Frequency Input. This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. Crystal Connection. Input connection for an external crystal. If using an external reference, this pin must be left unconnected. Spread Spectrum Control (Active LOW). Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. Modulation Width Selection. When Spread Spectrum feature is turned on, these pins are used to select the amount of variation and peak EMI reduction that is desired on the output signal. MW0:Down, MW1:Up, MW2:Down (see Table 2). Reference Frequency Selection. The logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors. Output Frequency Selection Bits. These pins select the frequency operation for the output. Refer to Table 1. The OR2 pin has an internal pull-up resistor. The OR1 pin has internal pull-down resistors. Clock Pin for SMBus Circuitry. Data Pin for SMBus Circuitry. Power Connection. Connected to 3.3V or 5V power supply. Analog Power Connection. Connected to 3.3V or 5V power supply. Ground Connection. Connect all ground pins to the common ground plane.
IR1:2
17, 16
I
OR1:2
6, 9
I
SCLK SData VDD AVDD GND
7 5 12, 19 3 8, 13, 18
I I/O P P G
Table 1. Frequency Configuration (Frequencies in MHz) Range of Fin Frequency Min. 14 14 14 25 25 25 50 50 50 Reserved Power-down Hi-Z Power-down 0 Power-down 1 Max. 41.7 41.7 41.7 83.3 83.3 83.3 166 166 166 Multiplier Settings OR2 0 1 1 0 1 1 0 1 1 0 0 0 0 OR1 1 0 1 1 0 1 1 0 1 0 0 0 0 1 2 4 0.5 1 2 0.25 0.5 1 N/A N/A N/A N/A Output/ Input Modulation and Range of Fout Required R Settings Power-down Settings Min. 14 28 56 13 25 50 13 25 50 N/A N/A N/A N/A Max. 41.7 83.3 166 41.7 83.3 166 41.7 83.3 166 N/A N/A N/A N/A IR2 0 0 0 1 1 1 1 1 1 As Set As Set As Set As Set IR1 1 1 1 0 0 0 1 1 1 As Set As Set As Set As Set 1 1 0 0 MW2 MW1 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 Table 2 0 1 0 1
Document #: 38-07124 Rev. *B
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CY25245
Table 2. Modulation Width Selection Table Bandwith Limit Frequencies as a % Value of Fout EMI Reduction Minimum EMI Control Suggested Setting Alternate Setting Maximum EMI reduction Modulation Setting MW2 0 0 1 1 MW1 0 1 0 1 Low 98.75% 97.5% 95.0% 90.0% MW0 = 0 High 100% 100% 100% 100% Low 99.375% 98.75% 97.5% 95% MW0 = 1 High 100.625% 101.25% 102.5% 105%
Overview
The CY25245 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. times the reference frequency.[3] The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In spread spectrum frequency timing generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS2:1 pins), the frequency range can be set (see Table 2). Spreading percentage is set with pins MW0:2 as shown in Table 2. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided.
Functional Description
The CY25245 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q
VDD Clock Input Reference Input Freq. Divider Q Phase Detector Charge Pump
Modulating Waveform
VCO
Post Dividers
CLKOUT (EMI suppressed)
Feedback Divider P
PLL
GND
Figure 1. Functional Block Diagram
Note: 3. For the CY25245, the output frequency is nominally equal to the input frequency.
Document #: 38-07124 Rev. *B
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CY25245
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2. As shown in Figure 2, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The output clock is modulated with a waveform depicted in Figure 3. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is as described in Table 2. Figure 3 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices.
EMI Reduction
Amplitude (dB)
Spread Spectrum Enabled
NonSpread Spectrum
Frequency Span (MHz) Down Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
10%
20%
30%
40%
50%
60%
70%
80%
100%
90%
MIN.
Figure 3. Typical Modulation Profile
Document #: 38-07124 Rev. *B
100%
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CY25245
Serial Data Interface
The CY25245 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the CY25245 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for Table 3. Serial Data Interface Control Functions Summary Control Function Description Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. power management functions. Table 3 summarizes the control functions of the serial data interface.
Operation
Data is written to the CY25245 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4. Writing Data Bytes Each bit in Data Bytes 0-7 control a particular device function except for the "reserved" bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 5 gives the bit formats for registers located in Data Bytes 0-7.
CPU Clock Frequency Provides CPU/PCI frequency selections through For alternate microprocessors and power Selection software. Frequency is changed in a smooth and management options. Smooth frequency transition controlled fashion. allows CPU frequency change under normal system operation. Spread Spectrum Enabling Output three-state (Reserved) Enables or disables spread spectrum clocking. Puts clock output into a high-impedance state. Reserved function for future device revision or production device testing. For EMI reduction. Production PCB testing. No user application. Register bit must be written as 0.
Table 4. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the CY25245 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the CY25245 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the CY25245, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the CY25245, therefore bit values are ignored ("don't care"). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus.
2
Command Code Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10 11
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7
Refer to Table 5 The data bits in Data Bytes 0-7 set internal CY25245 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map.
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CY25245
Table 5. Data Bytes 0-7 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1 0 Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 1 0 Data Byte 4 7 6 5 4 3 2 16 17 9 6 - - IR2 IR1 OR2 OR1 - - MSB of Input Range Select LSB of Input Range Select MSB of Output Range Select LSB of Output Range Select Hardware/Software Frequency Select Stop Function Refer to Table 1 Refer to Table 1 Refer to Table 1 Refer to Table 1 Hardware Normal Software Stop 0 1 1 0 0 0 Page 6 of 11 - - - - - - - - - - - - - - - - (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 Pin No. - - - - - - - - Pin Name - - - - - - - - (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Control Function 0 - - - - - - - - Data Byte 0 - - - - - - - - 0 0 0 0 0 0 0 0 Bit Control 1 Default
Document #: 38-07124 Rev. *B
CY25245
Table 5. Data Bytes 0-7 Serial Configuration Map (continued) Affected Pin Bit(s) 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 Data Byte 7 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 - - - - - - - - - - - - - - - - (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 11 14 20 15 - - - - MW2 MW1 REFOUT SSOUT - - - - MSB of Modulation Width Selection Modulation Width Selection Bit Output Enable Output Enable (Reserved) (Reserved) (Reserved) (Reserved) Refer to Table 2 Refer to Table 2 Disabled Disabled - - - - Enabled Enabled - - - - 0 1 1 1 0 0 0 0 Pin No. 10 4 Pin Name SSON# MW0 Control Function Spread Spectrum LSB of Modulation Width Selection 0 Spread On Bit Control 1 Spread Off Default 0 0
Refer to Table 2
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CY25245
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condiParameter VDD, VIN TSTG TA TB PD Description Voltage on Any Pin with Respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W
DC Electrical Characteristics: 0C < TA < 70C, VDD = 3.3V 0.3V[4]
Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power-up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-Up Resistor Clock Output Impedance 250 25 Note 4 Note 4 @ 0.4V, VDD = 3.3V @ 2.4V, VDD = 3.3V 2.4 -50 -50 15 15 7 50 50 2.4 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 18 Max. 32 5 0.8 Unit mA ms V V V V A A mA mA pF k
DC Electrical Characteristics: 0C < TA < 70C, VDD = 5V 10%
Parameter IDD tON VIL VIH VOL VOH IIL IIH IOL IOH CI RP ZOUT Description Supply Current Power-up Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Pull-up Resistor Clock Output Impedance 250 25 Note 4 Note 4 @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V 2.4 -50 -50 24 24 7 50 50 0.7VDD 0.4 First locked clock cycle after Power Good Test Condition Min. Typ. 30 Max. 50 5 0.15VDD Unit mA ms V V V V A A mA mA pF k
Note: 4. Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor.
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CY25245
AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V 0.3V or 5V10%
Parameter fIN fOUT tR tF tOD tID tJCYC Description Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-cycle Test Condition Input Clock Spread Off 15-pF load, 0.8V-2.4V 15-pF load, 2.4V-0.8V 15-pF load 40 40 250 Min. 14 13 2 2 Typ. Max. 166 166 5 5 60 60 300 Unit MHz MHz ns ns % % ps
Ordering Information
Ordering Code CY25245PVC CY25245PVCT Lead-free CY25245OXC CY25245OXCT 20-pin Plastic SSOP 20-pin Plastic SSOP --Tape and Reel Commercial, 0C to 70C Commercial, 0C to 70C Package Type 20-pin Plastic SSOP 20-pin Plastic SSOP --Tape and Reel Product Flow Commercial, 0C to 70C Commercial, 0C to 70C
Layout Example
+3.3V Supply FB
VDDQ3
F 0.005 F
C3 G
G
1
G
20
G V
2
G
19 18 17 16
G
CY25245
3 4 5 6 7 8 9
V G
G
G
15 14
G
G V G
13 12 11
G
10 G
Ceramic Caps C1 = 10-22 F C2 = 0.005 F
FB = Vishay ILB1206 - 300 (300 @ 100 MHz) or TDK ACB2012L-120 or Murata BLM21B601 G = VIA to GND plane layer V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 F ceramic.
Document #: 38-07124 Rev. *B
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CY25245
Package Drawing and Dimension
20-pin (5.3 mm) Shrunk Small Outline Package O20
51-85077-*C
PREMIS and SMARTSPREAD are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07124 Rev. *B
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY25245
Document History Page
Document Title: CY25245 Frequency-multiplying, Peak-reducing EMI Solution Document Number: 38-07124 REV. ** *A *B ECN NO. 109865 122550 318273 Issue Date 11/13/01 01/08/03 See ECN Orig. of Change IKA RGL RGL New data sheet Added SMARTSPREAD in the features area Added Lead-free devices Description of Change
Document #: 38-07124 Rev. *B
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